The uniform memory hierarchy model of computation

DOI10.1007/BF01185206zbMath0938.68638OpenAlexW1979219950MaRDI QIDQ1333430

T. Selker, L. Carter, Ephraim Feig, Bowen Alpern

Publication date: 21 June 2000

Published in: Algorithmica (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/bf01185206

zbMATH Keywords

FFTmemory hierarchyhigh-performance computingmatrix multiplicationmodel of computationbridging modelcache architectureperformance programming

Mathematics Subject Classification ID

Related Items (11)

Methods for message routing in parallel machines ⋮ Algorithms for parallel memory. II: Hierarchical multilevel memories ⋮ The latency-of-data-access model for analyzing parallel computation ⋮ MODELS AND RESOURCE METRICS FOR PARALLEL AND DISTRIBUTED COMPUTATION∗ ⋮ A bridging model for multi-core computing ⋮ Turing machines with two-level memory: a deep look into the input/output complexity ⋮ Turing machines with two-level memory: new computational models for analyzing the input/output complexity ⋮ The cost of cache-oblivious searching ⋮ On the limits of cache-oblivious rational permutations ⋮ A blocked all-pairs shortest-paths algorithm ⋮ Bicriteria Data Compression

Uses Software

• LAPACK
• CLAPACK
• BLAS
• ESSL

Cites Work

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• Algorithms for parallel memory. II: Hierarchical multilevel memories
• The program dependence graph and its use in optimization
• Organizing matrices and matrix operations for paged memory systems

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