Method of constructing parallel forms of algorithms based on locally parallel, globally sequential partition

DOI10.1007/BF02366530zbMATH Open0879.68057OpenAlexW2021179831MaRDI QIDQ1364074FDOQ1364074

Authors: N. A. Likhoded, A. A. Tiunchik 

Publication date: 12 January 1998

Published in: Cybernetics and Systems Analysis (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/bf02366530

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zbMATH Keywords

global interconnectionsVLSI processors

Mathematics Subject Classification ID

Distributed algorithms (68W15) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

Cites Work

• Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays

Cited In (5)

• Title not available (Why is that?)
• Localized algorithms for vlsi processor arrays
• Title not available (Why is that?)
• Title not available (Why is that?)
• Localization of edges in graph models of two-level algorithms

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