Architecture of modern RISC-microprocessors

DOI10.1007/S002870050071zbMATH Open1034.68503OpenAlexW4235970459MaRDI QIDQ1374797FDOQ1374797

Authors: Hans Eberle 

Publication date: 10 December 1997

Published in: Informatik Spektrum (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s002870050071

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zbMATH Keywords

RISCmicroprocessorCachePipeline process

Mathematics Subject Classification ID

Computer system organization (68M99)

Cited In (9)

• MMIXware. A RISC computer for the third millennium.
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• A software instruction prefetching method in architectures with static scheduling
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• Optimizing pipeline for a RISC processor with multimedia extension ISA
• The dawn of a new era in processor evolution

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