Further reducing the redundancy of a notation over a minimally redundant digit set

DOI10.1023/A:1021133616373zbMath1039.68005OpenAlexW1592138822MaRDI QIDQ1405453

David W. Matula, Marc Daumas

Publication date: 25 August 2003

Published in: Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1023/a:1021133616373

zbMATH Keywords

additionmultiplicationcomputer arithmeticredundant notation

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07)

Related Items (1)

An efficient universal addition scheme for all hybrid-redundant representations with weighted bit-set encoding

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