Implementation of RNS-based distributed arithmetic discrete wavelet transform architectures using field-programmable logic

DOI10.1023/A:1021158221825zbMATH Open1039.68010MaRDI QIDQ1405481FDOQ1405481

Authors: D. Massart 

Publication date: 25 August 2003

Published in: Journal of VLSI signal processing systems for signal, image and video technology (Search for Journal in Brave)

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zbMATH Keywords

residue number systemdiscrete wavelet transformdigital signal processingdistributed arithmeticfield-programmable logic

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07)

Cited In (8)

• Title not available (Why is that?)
• Design and implementation of high-performance RNS wavelet processors using custom IC technologies
• A low-power two-digit multi-dimensional logarithmic number system filterbank architecture for a digital hearing aid
• RNS architectures for the implementation of the `diagonal function'
• A distributed arithmetic and polyphase decomposition FPGA implementation of the discrete wavelet transform
• A modular approach to the computation of convolution sum using distributed arithmetic principles
• Implementation of a communications channelizer using FPGAs and RNS arithmetic
• Title not available (Why is that?)

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