A quantitative analysis of tile size selection algorithms
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Publication:1426947
DOI10.1023/B:SUPE.0000011388.54204.8ezbMath1057.68130MaRDI QIDQ1426947
Ulrich Kremer, Chung-hsing Hsu
Publication date: 15 March 2004
Published in: The Journal of Supercomputing (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1023/b:supe.0000011388.54204.8e
loop tiling; compiler optimizations; performance models; array padding; memory hierarchy optimization; quantitative case study