VLSI implementation of the multistage detector for next generation wideband CDMA receivers

DOI10.1023/A:1014086523082MaRDI QIDQ1597576zbMATH OpenOpenAlexFDO

Authors Gang Xu, Sridhar Rajagopal, Joseph R. Cavallaro, Behnaam Aazhang

Publication date 30 May 2002

Published in Journal of VLSI signal processing systems for signal, image and video technology (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1023/a:1014086523082

zbMATH Keywords

multistage detection algorithmwidemand code division multiple access

Mathematics Subject Classification ID

Network design and communication in computer systems (68M10) Computing methodologies and applications (68U99) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

Recommendations

• Efficient VLSI architectures for multiuser channel estimation in wireless base-station receivers
• A Systematic Approach to Multistage Detectors in Multipath Fading Channels
• scientific article; zbMATH DE number 5778136
• DS/CDMA Successive Interference Cancellation
• Robust multiuser detection based on variable loading RLS technique

Cited in

(2)

• Efficient VLSI architectures for multiuser channel estimation in wireless base-station receivers
• A low complexity and low power SoC design architecture for adaptive MAI suppression in CDMA systems

This page was built for publication: VLSI implementation of the multistage detector for next generation wideband CDMA receivers

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q1597576)