Automatic intra-register vectorization for the Intel^ architecture

DOI10.1023/A:1014230429447zbMATH Open1014.68048OpenAlexW1495550651MaRDI QIDQ1604705FDOQ1604705

Authors: Aart J. C. Bik, Milind Girkar, Paul M. Grey, Xinmin Tian 

Publication date: 8 July 2002

Published in: International Journal of Parallel Programming (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1023/a:1014230429447

Recommendations

• Compiler Construction
• scientific article; zbMATH DE number 1282861
• Compilation techniques for high level parallel code
• scientific article; zbMATH DE number 1863261
• Automatic SIMD vectorization for Haskell

zbMATH Keywords

compilerSIMD

Mathematics Subject Classification ID

Theory of compilers and interpreters (68N20)

Cited In (10)

• Pseudo-Vectorization and RISC Optimization Techniques for the Hitachi SR8000 Architecture
• Automatic SIMD vectorization for Haskell
• Title not available (Why is that?)
• Title not available (Why is that?)
• Semi-automatic composition of loop transformations for deep parallelism and memory hierarchies
• Title not available (Why is that?)
• Automatic application-specific instruction-set extensions under microarchitectural constraints
• ParVec: vectorizing the PARSEC benchmark suite
• Efficient SIMD optimization for media processors
• Exploiting vector instructions with generalized stream fusion

This page was built for publication: Automatic intra-register vectorization for the Intel\(^\circledR\) architecture

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q1604705)