Verification of arithmetic circuits using binary moment diagrams

DOI10.1007/S100090100037MaRDI QIDQ1606802zbMATH OpenOpenAlexWikidataFDO

Authors Randal E. Bryant, Yirng-An Chen

Publication date 25 July 2002

Published in International Journal on Software Tools for Technology Transfer. STTT (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/s100090100037

Mathematics Subject Classification ID

Network design and communication in computer systems (68M10) Computer science aspects of computer-aided design (68U07) Computing methodologies and applications (68U99)

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Cited in

(7)

• Polynomial formal verification of multipliers
• Incremental column-wise verification of arithmetic circuits using computer algebra
• Decision diagrams for verification
• Formal Verification of Integer Multiplier Circuits Using Algebraic Reasoning: A Survey
• Bit-precise verification of discontinuity errors under fixed-point arithmetic
• Symbolic computer algebra for multipliers revisited - demonstrating the significance of order and phase optimization
• Divider verification using symbolic computer algebra and delayed don't care optimization: theory and practical implementation

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