Boolean approaches to graph embeddings related to VLSI

DOI10.1007/BF02878978zbMath1002.68115OpenAlexW146077645MaRDI QIDQ1609705

Yanpei Liu

Publication date: 15 August 2002

Published in: Science in China. Series A (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/bf02878978

zbMATH Keywords

VLSIgraph embeddingsBoolean equationrectilinear layout

Mathematics Subject Classification ID

Graph theory (including graph drawing) in computer science (68R10) Planar graphs; geometric and topological aspects of graph theory (05C10) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

Related Items (1)

Orthogonal drawings of graphs for the automation of VLSI circuit design

Cites Work

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• General theoretical results on rectilinear embeddability of graphs
• Theoretical results on at most 1-bend embeddability of graphs
• Some combinatorial optimization problems arising from VLSI circuit design
• At most single-bend embeddings of cubic graphs
• A graph partition problem
• A linear algorithm for 2-bend embeddings of planar graphs in the two-dimensional grid
• On Boolean characterizations of planarity and planar embeddings of graphs
• Boolean planarity characterization of graphs
• Boolean approach to planar embeddings of a graph

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