Boolean approaches to graph embeddings related to VLSI

DOI10.1007/BF02878978MaRDI QIDQ1609705zbMATHOpenAlexFDO

Authors Yanpei Liu

Publication date 15 August 2002

Published in Science in China. Series A (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/bf02878978

zbMATH Keywords

graph embeddingsVLSIBoolean equationrectilinear layout

Mathematics Subject Classification ID

Graph theory (including graph drawing) in computer science (68R10) Planar graphs; geometric and topological aspects of graph theory (05C10) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

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Cites work

• scientific article; zbMATH DE number 951476 (Why is no real title available?)
• scientific article; zbMATH DE number 279581 (Why is no real title available?)
• A graph partition problem
• A linear algorithm for 2-bend embeddings of planar graphs in the two-dimensional grid
• At most single-bend embeddings of cubic graphs
• Boolean approach to planar embeddings of a graph
• Boolean planarity characterization of graphs
• General theoretical results on rectilinear embeddability of graphs
• On Boolean characterizations of planarity and planar embeddings of graphs
• Optimally extending bistandard graphs on the orthogonal grid (extended abstract)
• Some combinatorial optimization problems arising from VLSI circuit design
• Theoretical results on at most 1-bend embeddability of graphs

Cited in

(3)

• scientific article; zbMATH DE number 822063 (Why is no real title available?)
• Application of graph theory to topology generation for logic gates
• Orthogonal drawings of graphs for the automation of VLSI circuit design

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