Modular deductive verification of multiprocessor hardware designs
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Publication:1702892
DOI10.1007/978-3-319-21668-3_7zbMath1381.68183MaRDI QIDQ1702892
Adam Chlipala, Nirav Dave, Muralidaran Vijayaraghavan, Arvind
Publication date: 1 March 2018
Full work available at URL: https://doi.org/10.1007/978-3-319-21668-3_7
68Q60: Specification and verification (program logics, model checking, etc.)
68Q85: Models and methods for concurrent and distributed computing (process algebras, bisimulation, transition nets, etc.)
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