A methodology for speeding up loop kernels by exploiting the software information and the memory architecture
From MaRDI portal
(Redirected from Publication:1749110)
Recommendations
- A methodology pruning the search space of six compiler transformations by addressing them together as one problem and by exploiting the hardware architecture details
- Transforming complex loop nests for locality
- Loop transformations, convexity, pruning and optimization
- Optimized unrolling of nested loops
- Software pipelining of loops by the method of modulo scheduling
Cites work
- A Methodology for Speeding Up Fast Fourier Transform Focusing on Memory Architecture Utilization
- A methodology for speeding up loop kernels by exploiting the software information and the memory architecture
- Adaptive optimizing compilers for the 21st century
- Data Structures and Algorithms
- scientific article; zbMATH DE number 1943827 (Why is no real title available?)
- scientific article; zbMATH DE number 1984687 (Why is no real title available?)
- Optimal register allocation for SSA-form programs in polynomial time
Cited in
(4)- A methodology pruning the search space of six compiler transformations by addressing them together as one problem and by exploiting the hardware architecture details
- A methodology for speeding up loop kernels by exploiting the software information and the memory architecture
- Loop-Based Instruction Prefetching to Reduce the Worst-Case Execution Time
- Some Notes on Speeding Up Certain Loops by Software, Firmware, and Hardware Means
This page was built for publication: A methodology for speeding up loop kernels by exploiting the software information and the memory architecture
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q1749110)
