An optimal emulator and VLSI layout for complete binary trees

DOI10.1007/S002360050093zbMATH Open0865.68085OpenAlexW1977119748MaRDI QIDQ1920223FDOQ1920223

Authors: Nancy Eleser, Kemal Efe 

Publication date: 25 September 1996

Published in: Acta Informatica (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s002360050093

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zbMATH Keywords

binary treesgraph embeddingparallel architecturesVLSI layout

Mathematics Subject Classification ID

Trees (05C05) Graph theory (including graph drawing) in computer science (68R10) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

Cited In (6)

• Embedding ternary trees in VLSI arrays
• Expansion of layouts of complete binary trees into grids
• VLSI layouts of complete graphs and star graphs
• Efficient Embeddings of Binary Trees in VLSI Arrays
• Title not available (Why is that?)
• On the maximum edge length in VLSI layouts of complete binary trees

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