Information-flow control on ARM and POWER multicore processors
From MaRDI portal
Publication:2147697
Recommendations
- Verification of Concurrent Programs on Weak Memory Models
- scientific article; zbMATH DE number 1759625
- Parallelized sequential composition and hardware weak memory models
- Security for multithreaded programs under cooperative scheduling
- Securing interaction between threads and the scheduler in the presence of synchronization
Cites work
- scientific article; zbMATH DE number 7649976 (Why is no real title available?)
- A promising semantics for relaxed-memory concurrency
- A wide-spectrum language for verification of programs on weak memory models
- An axiomatic basis for computer programming
- Dependent information flow types
- Information Security and Cryptology - ICISC 2005
- Isabelle/HOL. A proof assistant for higher-order logic
- The verified CakeML compiler backend
- Tools and algorithms for the construction and analysis of systems. 14th international conference, TACAS 2008, held as part of the joint European conferences on theory and practice of software, ETAPS 2008, Budapest, Hungary, March 29--April 6, 2008. Proceedings
This page was built for publication: Information-flow control on ARM and POWER multicore processors
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q2147697)