Reduced checking sequences using unreliable reset

DOI10.1016/J.IPL.2015.01.002zbMATH Open1327.68160OpenAlexW2028233775MaRDI QIDQ2339596FDOQ2339596

Authors: Guy-Vincent Jourdan, Hasan Ural, Hüsnü Yenigün 

Publication date: 2 April 2015

Published in: Information Processing Letters (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/j.ipl.2015.01.002

Recommendations

• Checking sequence generation for symbolic input/output FSMs by constraint solving
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zbMATH Keywords

formal methodssynchronizing sequencesmodel-based testingfinite state machineschecking sequences

Mathematics Subject Classification ID

Formal languages and automata (68Q45) Specification and verification (program logics, model checking, etc.) (68Q60)

Cites Work

• Model-based testing of reactive systems. Advanced lectures.
• Testing Software Design Modeled by Finite-State Machines
• Title not available (Why is that?)
• On the Probability of Being Synchronizable
• Testing finite-state machines: state identification and verification
• Testing finite state machines: Fault detection

Cited In (5)

• Reducing the Lengths of Checking Sequences by Overlapping
• Using Distinguishing and UIO Sequences Together in a Checking Sequence
• Reduced length checking sequences
• DCCP partial reliability extension with sequence number compensation
• Deriving Homing Sequences for Finite State Machines with Timed Guards

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