Compaction of test response at self-testing in the programmable logic matrices

DOI10.1134/S0005117913020082MaRDI QIDQ2392441zbMATH OpenOpenAlexFDO

Authors G. P. Aksenova

Publication date 1 August 2013

Published in Automation and Remote Control (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1134/s0005117913020082

zbMATH Keywords

amount of self-testing hardwarecontrollable architecturemod 2 convolution schemesprogrammable logic matrix

Mathematics Subject Classification ID

Control/observation systems governed by functional relations other than differential equations (such as hybrid and switching systems) (93C30) Application models in control theory (93C95)

Recommendations

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Cites work

• The method of parallel-sequential built-in self-testing in integrated circuits of the type sFPGAs

Cited in

(4)

• Self-testing automaton networks: their design in programmable logical matrices
• scientific article; zbMATH DE number 4181295 (Why is no real title available?)
• Programmable BIST space compactors
• Response compaction for system-on-a-chip based on advanced convolutional codes

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