A compact DSP core with static floating-point arithmetic

DOI10.1007/S11265-005-4178-5zbMath1103.68304OpenAlexW2170840568MaRDI QIDQ2432118

Chih-Wei Liu, Chih-Wei Jen, Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao

Publication date: 25 October 2006

Published in: Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s11265-005-4178-5

zbMATH Keywords

signal processing

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07)

Uses Software

• LINDO

Cites Work

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• Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing

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