Provably-correct hardware compilation tools based on pass separation techniques

DOI10.1007/S00165-005-0075-8MaRDI QIDQ2432229zbMATH OpenOpenAlexFDO

Authors Steve McKeever, Wayne Luk

Publication date 25 October 2006

Published in Formal Aspects of Computing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/s00165-005-0075-8

zbMATH Keywords

flattening procedurerelative placement methodstructural VHDL

Mathematics Subject Classification ID

Theory of compilers and interpreters (68N20)

Recommendations

• scientific article; zbMATH DE number 1852160
• scientific article; zbMATH DE number 1979560
• Verification of FPGA layout generators in higher-order logic
• Publication:4942020
• Formal verification for high-assurance behavioral synthesis

Cited in

(3)

• scientific article; zbMATH DE number 1852160 (Why is no real title available?)
• scientific article; zbMATH DE number 1979560 (Why is no real title available?)
• Verification of FPGA layout generators in higher-order logic

This page was built for publication: Provably-correct hardware compilation tools based on pass separation techniques

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q2432229)