On VLSI interconnect optimization and linear ordering problem
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Publication:2443401
DOI10.1007/s11081-010-9128-9zbMath1284.94168MaRDI QIDQ2443401
Shmuel Wimer, Avinoam Kolodny, Konstantin Moiseev
Publication date: 7 April 2014
Published in: Optimization and Engineering (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1007/s11081-010-9128-9
delay minimization; linear ordering problem; power minimization; optimal permutation; VLSI interconnects optimization
94C99: Circuits, networks
Uses Software
Cites Work
- The complexity of VLSI power-delay optimization by interconnect resizing
- Intensification and diversification with elite tabu search solutions for the linear ordering problem
- An experimental evaluation of a scatter search for the linear ordering problem
- Variable neighborhood search for the linear ordering problem
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