A novel design of 8-bit adder/subtractor by quantum-dot cellular automata

DOI10.1016/J.JCSS.2014.04.012zbMATH Open1311.68092OpenAlexW2054694714MaRDI QIDQ2453560FDOQ2453560

Authors: Moein Kianpour, Reza Sabbaghi-Nadooshan, Keivan Navi 

Publication date: 10 June 2014

Published in: Journal of Computer and System Sciences (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/j.jcss.2014.04.012

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zbMATH Keywords

adderquantum-dot cellular automata (QCA)majority gatesubtractorexclusive OR (XOR) gate

Mathematics Subject Classification ID

Cellular automata (computational aspects) (68Q80)

Cites Work

• Irreversibility and Heat Generation in the Computing Process
• Logical Reversibility of Computation
• Adder and Multiplier Design in Quantum-Dot Cellular Automata
• Intrinsically universal \(n\)-dimensional quantum cellular automata

Cited In (13)

• A power-efficient single layer full adder design in field-coupled QCA nanocomputing
• Robust coplanar full adder based on novel inverter in quantum cellular automata
• A novel full adder/subtractor in quantum-dot cellular automata
• An optimized three-level design of decoder based on nanoscale quantum-dot cellular automata
• Design of low-complexity and high-speed coplanar four-bit ripple carry adder in QCA technology
• Designing nanoscale counter using reversible gate based on quantum-dot cellular automata
• A three-layer full adder/subtractor structure in quantum-dot cellular automata
• Fault-tolerant design of a shift register at the nanoscale based on quantum-dot cellular automata
• QCA Gray code converter circuits using LTEx methodology
• Implementing a one-bit reversible full adder using quantum-dot cellular automata
• A novel adder circuit design in quantum-dot cellular automata technology
• A coplanar XOR using NAND-NOR-inverter and five-input majority voter in quantum-dot cellular automata technology
• Fast quantum-dot cellular automata adder/subtractor using novel fault tolerant exclusive-or gate and full adder

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