An astatic phase-locked system for digital signal processors: circuit design and stability
From MaRDI portal
Publication:2487550
DOI10.1007/S10513-005-0064-7zbMATH Open1075.94028OpenAlexW2081968389MaRDI QIDQ2487550FDOQ2487550
Authors: S. M. Seledzhi, G. A. Leonov
Publication date: 8 August 2005
Published in: Automation and Remote Control (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1007/s10513-005-0064-7
Recommendations
Cites Work
Cited In (7)
- PLL-based digital control with Åstrom-Hägglund tuning
- Title not available (Why is that?)
- Implementation and stability study of phase-locked-loop nonlinear dynamic measurement systems
- Global stability of discrete phase-locked loops
- Mathematical models of phase syncronization systems with quadrature and phase-quadrature units
- Analysis and synthesis of controlled delay lines
- STABILITY AND BIFURCATIONS OF PHASE-LOCKED LOOPS FOR DIGITAL SIGNAL PROCESSORS
This page was built for publication: An astatic phase-locked system for digital signal processors: circuit design and stability
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q2487550)