Using graph models in retargetable optimizing compilers for microprocessors with VLIW architectures

DOI10.1023/A:1024735105533zbMATH Open1074.68544OpenAlexW1524661456MaRDI QIDQ2487876FDOQ2487876

Authors: A. E. Doroshenko, D. V. Ragozin 

Publication date: 12 August 2005

Published in: Cybernetics and Systems Analysis (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1023/a:1024735105533

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zbMATH Keywords

digital signal processingoptimizing compilergraph models of programsretargetable code generatorVLIW architecture of microprocessors

Mathematics Subject Classification ID

Theory of compilers and interpreters (68N20) Computer system organization (68M99)

Cited In (1)

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