Extended lock range zero-crossing digital phase-locked loop with time delay
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Publication:2501738
DOI10.1155/WCN.2005.413zbMath1123.93318WikidataQ59148892 ScholiaQ59148892MaRDI QIDQ2501738
Publication date: 12 September 2006
Published in: EURASIP Journal on Wireless Communications and Networking (Search for Journal in Brave)
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