New VLSI architectures for three-level correlators

DOI10.1007/BF01188989zbMath0860.68013OpenAlexW2053903961MaRDI QIDQ2563558

Saleh A. Alshebeili, Rana Ejaz Ahmed

Publication date: 26 January 1997

Published in: Circuits, Systems, and Signal Processing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/bf01188989

zbMATH Keywords

VLSI architectures

Mathematics Subject Classification ID

Computer system organization (68M99)

Cites Work

• The use of a high sampling rate and ternary quantization to improve the performance of the random reference correlator (Corresp.)
• Modified digital correlator and its estimation errors

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