FPGA-based configurable systolic architecture for window-based image processing

DOI10.1155/ASP.2005.1024zbMath1107.94324OpenAlexW2143188228MaRDI QIDQ2570541

Miguel Arias-Estrada, César Torres-Huitzil

Publication date: 28 October 2005

Published in: EURASIP Journal on Applied Signal Processing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1155/asp.2005.1024

zbMATH Keywords

real timesystolic arrayFPGA configurable systemwindow-based image processing

Mathematics Subject Classification ID

Image processing (compression, reconstruction, etc.) in information and communication theory (94A08)

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