FPGA-based configurable systolic architecture for window-based image processing

DOI10.1155/ASP.2005.1024zbMATH Open1107.94324OpenAlexW2143188228MaRDI QIDQ2570541FDOQ2570541

Authors: César Torres-Huitzil, Miguel Arias-Estrada 

Publication date: 28 October 2005

Published in: EURASIP Journal on Applied Signal Processing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1155/asp.2005.1024

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zbMATH Keywords

real timesystolic arrayFPGA configurable systemwindow-based image processing

Mathematics Subject Classification ID

Image processing (compression, reconstruction, etc.) in information and communication theory (94A08)

Cited In (5)

• Towards a general framework for FPGA based image processing using hardware skeletons
• FPGA implementation of a geometric voting scheme for the extraction of geometric entities from images
• A New FPGA/DSP-Based Parallel Architecture for Real-Time Image Processing
• Title not available (Why is that?)
• Two-dimensional signal processing based on FPGA

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