Memory controllers for mixed-time-criticality systems. Architectures, methodologies and trade-offs

DOI10.1007/978-3-319-32094-6zbMATH Open1336.68002OpenAlexW4230467361MaRDI QIDQ2808229FDOQ2808229

Sven Goossens, Kees Goossens, Karthik Chandrasekar, Benny Akesson

Publication date: 20 May 2016

Published in: Embedded Systems (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/978-3-319-32094-6

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Mathematics Subject Classification ID

Research exposition (monographs, survey articles) pertaining to computer science (68-02) Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Reliability, testing and fault tolerance of networks and computer systems (68M15) Mathematical problems of computer architecture (68M07)

Cited In (2)

• Title not available (Why is that?)
• A Globally Arbitrated Memory Tree for Mixed-Time-Criticality Systems

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