The higher order Hausdorff Voronoi diagram and VLSI critical area extraction for via-blocks

MaRDI QIDQ2948438zbMATH OpenFDO

Authors Evanthia Papadopoulou

Publication date 30 September 2015

zbMATH Keywords

Hausdorff Voronoi diagramdesign for manufacturingVLSI yield predictionrandom manufacturing defectsVLSI critical area analysisVoronoï diagram

Mathematics Subject Classification ID

Computer graphics; computational geometry (digital and algorithmic aspects) (68U05) Combinatorial complexity of geometric structures (52C45)

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(6)

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• VORONOI DIAGRAM OF A POLYGON IN CHESSBOARD METRIC AND MASKLESS LITHOGRAPHIC APPLICATIONS
• On the Hausdorff Voronoi diagram of point clusters in the plane.
• Higher Order Voronoi Diagrams of Segments for VLSI Critical Area Extraction
• Map of geometric minimal cuts for general planar embedding
• THE HAUSDORFF VORONOI DIAGRAM OF POLYGONAL OBJECTS: A DIVIDE AND CONQUER APPROACH

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