The higher order Hausdorff Voronoi diagram and VLSI critical area extraction for via-blocks

zbMATH Open1325.52017MaRDI QIDQ2948438FDOQ2948438

Authors: Evanthia Papadopoulou 

Publication date: 30 September 2015

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zbMATH Keywords

Hausdorff Voronoi diagramdesign for manufacturingVLSI yield predictionrandom manufacturing defectsVLSI critical area analysisVoronoï diagram

Mathematics Subject Classification ID

Computer graphics; computational geometry (digital and algorithmic aspects) (68U05) Combinatorial complexity of geometric structures (52C45)

Cited In (6)

• THE L_∞ VORONOI DIAGRAM OF SEGMENTS AND VLSI APPLICATIONS
• On the Hausdorff Voronoi diagram of point clusters in the plane.
• VORONOI DIAGRAM OF A POLYGON IN CHESSBOARD METRIC AND MASKLESS LITHOGRAPHIC APPLICATIONS
• Higher Order Voronoi Diagrams of Segments for VLSI Critical Area Extraction
• THE HAUSDORFF VORONOI DIAGRAM OF POLYGONAL OBJECTS: A DIVIDE AND CONQUER APPROACH
• Map of geometric minimal cuts for general planar embedding

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