Designing a Resilient L1 Cache Architecture to Process Variation-Induced Access-Time Failures

DOI10.1109/TC.2015.2513771zbMATH Open1360.68050MaRDI QIDQ2985237FDOQ2985237

Authors: Seok-In Hong, Soontae Kim 

Publication date: 16 May 2017

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07)

Cited In (1)

• On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors

This page was built for publication: Designing a Resilient L1 Cache Architecture to Process Variation-Induced Access-Time Failures

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q2985237)