Low-power LDPC decoding by exploiting the fault-tolerance of the sum-product algorithm

zbMATH Open1221.94003MaRDI QIDQ3000910FDOQ3000910

Authors: Vincent Gaudet 

Publication date: 31 May 2011

Recommendations

• LP Decoding Corrects a Constant Fraction of Errors
• A low complexity LDPC decoder with a modified sum-product algorithm
• On Decoding of Low-Density Parity-Check Codes Over the Binary Erasure Channel
• scientific article
• An FPGA implementation of \((3,6)\)-regular low-density parity-check code decoder

zbMATH Keywords

sum-product algorithmiterative decodinglow-density parity-check codeserror-control codesforward error controllow-density parity-check decoding algorithmsvery large-scale integration

Mathematics Subject Classification ID

Communication theory (94A05) Fault detection; testing in circuits and networks (94C12) Decoding (94B35)

Cited In (1)

• A novel design methodology for high-performance programmable decoder cores for AA-LDPC codes

This page was built for publication: Low-power LDPC decoding by exploiting the fault-tolerance of the sum-product algorithm

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q3000910)