An exploration of mechanisms for dynamic cryptographic instruction set extension

DOI10.1007/978-3-642-23951-9_1zbMATH Open1401.94157OpenAlexW2123424088MaRDI QIDQ3172960FDOQ3172960

Authors: Philipp Grabher, Johann Großschädl, Simon Hoerder, Kimmo Järvinen, Stefan Tillich, M. Wójcik, Dan Page 

Publication date: 7 October 2011

Published in: Cryptographic hardware and embedded systems -- CHES 2011. 13th international workshop, Nara, Japan, September 28--October 1, 2011. Proceedings (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/978-3-642-23951-9_1

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zbMATH Keywords

FPGAembedded processorinstruction set extension

Mathematics Subject Classification ID

Data encryption (aspects in computer science) (68P25) Cryptography (94A60)

Cited In (2)

• A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions
• Certified compilation for cryptography: extended x86 instructions and constant-time verification

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