Parametric Deadlock-Freeness Checking Timed Automata

DOI10.1007/978-3-319-46750-4_27MaRDI QIDQ3179417zbMATH OpenOpenAlexFDO

Authors Étienne André

Publication date 21 December 2016

Published in Theoretical Aspects of Computing – ICTAC 2016 (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/978-3-319-46750-4_27

Mathematics Subject Classification ID

Formal languages and automata (68Q45) Specification and verification (program logics, model checking, etc.) (68Q60) Models and methods for concurrent and distributed computing (process algebras, bisimulation, transition nets, etc.) (68Q85)

Recommendations

• Bounded Model Checking for Parametric Timed Automata
• Durations and parametric model-checking in timed automata
• scientific article; zbMATH DE number 1701759
• Linear parametric model checking of timed automata
• Formal Modeling and Analysis of Timed Systems
• Reachability and liveness in parametric timed automata
• Verification of timed automata via satisfiability checking
• Parameterised model checking for alternating-time temporal logic
• Model-checking timed automata with deadlines with Uppaal

Cites work

• scientific article; zbMATH DE number 5175527 (Why is no real title available?)
• A theory of timed automata
• Integer Parameter Synthesis for Timed Automata
• Language emptiness of continuous-time parametric timed automata
• Linear parametric model checking of timed automata
• Parametric real-time reasoning
• Uppaal in a nutshell

Cited in

(6)

• Safe decomposition of startup requirements: verification and synthesis
• \textsf{IMITATOR} 3: synthesis of timing parameters beyond decidability
• Formal Approaches to Software Testing
• Distributed parametric model checking timed automata under non-zenoness assumption
• Checking deadlock-freedom of parametric component-based systems
• The automatic detection of token structures and invariants using SAT checking

Describes a project that uses

Uses Software

• IMITATOR
• Uppaal
• PPL
• PAT

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