Parametric Deadlock-Freeness Checking Timed Automata
DOI10.1007/978-3-319-46750-4_27zbMATH Open1482.68132OpenAlexW2522219859MaRDI QIDQ3179417FDOQ3179417
Authors: Étienne André 
Publication date: 21 December 2016
Published in: Theoretical Aspects of Computing – ICTAC 2016 (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1007/978-3-319-46750-4_27
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Cites Work
Cited In (6)
- Safe decomposition of startup requirements: verification and synthesis
- \textsf{IMITATOR} 3: synthesis of timing parameters beyond decidability
- Checking deadlock-freedom of parametric component-based systems
- Distributed parametric model checking timed automata under non-zenoness assumption
- Formal Approaches to Software Testing
- The automatic detection of token structures and invariants using SAT checking
Uses Software
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