A Parallel Architecture for Digital Filtering Using Fermat Number Transforms

DOI10.1109/TC.1983.1676339zbMath0534.94013MaRDI QIDQ3318687

Chiunn- Shyong Yeh, Howard M. Shao, Trieu-Kien Truong, Irving S. Reed

Publication date: 1983

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tc.1983.1676339

zbMATH Keywords

VLSI; digital filter; cyclic convolution; Fermat number transform; pipeline; overlap-save method

Mathematics Subject Classification ID

11T99: Finite fields and commutative rings (number-theoretic aspects)

94A99: Communication, information

94B99: Theory of error-correcting codes and error-detecting codes

68N25: Theory of operating systems

68W99: Algorithms in computer science