An Architecture for Bitonic Sorting with Optimal VLSI Performnance
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Publication:3323284
DOI10.1109/TC.1984.5009338zbMath0537.68062OpenAlexW2070265306MaRDI QIDQ3323284
Gianfranco Bilardi, Franco P. Preparata
Publication date: 1984
Published in: IEEE Transactions on Computers (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1109/tc.1984.5009338
parallel computationinterconnection networkoptimal algorithmsarea-time tradeoffVLSI complexitypleated cube-connected cyclesstable bitonic sorting
Analysis of algorithms and problem complexity (68Q25) Searching and sorting (68P10) Circuits, networks (94C99)
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