AN ANNEALING-BASED CIRCUIT PARTITIONER FOR HYPERCUBE ARCHITECTURE: DESIGN AND PERFORMANCE EVALUATION

DOI10.1142/S0129053390000066MaRDI QIDQ3348460zbMATH OpenFDO

Authors

Publication date 1990

Published in International Journal of High Speed Computing (Search for Journal in Brave)

zbMATH Keywords

simulated annealingcircuit simulationcircuit partitioninghypercube architecture

Mathematics Subject Classification ID

Circuits, networks (94C99) Performance evaluation, queueing, and scheduling in the context of computer systems (68M20)

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Cited in

(2)

• Parallel physical optimization algorithms for allocating data to multicomputer nodes
• Circuit partitioning using mean field annealing

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