AN ANNEALING-BASED CIRCUIT PARTITIONER FOR HYPERCUBE ARCHITECTURE: DESIGN AND PERFORMANCE EVALUATION
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Publication:3348460
DOI10.1142/S0129053390000066zbMath0726.68089MaRDI QIDQ3348460
No author found.
Publication date: 1990
Published in: International Journal of High Speed Computing (Search for Journal in Brave)
Circuits, networks (94C99) Performance evaluation, queueing, and scheduling in the context of computer systems (68M20)
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