Designing Predictable Cache Coherence Protocols for Multi-Core Real-Time Systems

DOI10.1109/TC.2020.3037747MaRDI QIDQ3390201zbMATH OpenOpenAlexFDO

Authors

Publication date 24 March 2022

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tc.2020.3037747

Mathematics Subject Classification ID

Computer science (68-XX)

Recommendations

• Deriving efficient cache coherence protocols through refinement
• Software-controlled cache coherence protocol for multicache systems

Cited in

(3)

• TACLC: Timing-Aware Cache Leakage Control for Hard Real-Time Systems
• Cache coherence requirements for interprocess rendezvous
• Deriving efficient cache coherence protocols through refinement

This page was built for publication: Designing Predictable Cache Coherence Protocols for Multi-Core Real-Time Systems

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q3390201)