Minimal linear equivalent analysis of a variable-memory binary sequence generator

DOI10.1109/18.50390MaRDI QIDQ3481641zbMATH OpenOpenAlexFDO

Authors Miodrag J. Mihaljević, J. Dj. Golić

Publication date 1990

Published in IEEE Transactions on Information Theory (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/18.50390

zbMATH Keywords

linear feedback shift registersvariable memorybinary sequence generatorfast binary sequences of large period and linear complexitymemory-based nonlinear generatorspread-spectrum and cryptographic applications

Mathematics Subject Classification ID

Shift register sequences and sequences over finite alphabets in information and communication theory (94A55) Communication, information (94A99)

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Cited in

(4)

• Edit distance correlation attacks on clock-controlled combiners with memory
• On period of multiplexed sequences
• The Number of Output Sequences of a Binary Sequence Generator
• Analysis of a Nonlinear Feedforward Logic for Binary Sequence Generators

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