FAULT TOLERANCE AND DETECTION IN CHAOTIC COMPUTERS

DOI10.1142/S0218127407018142zbMath1141.68013MaRDI QIDQ3510207

Sudeshna Sinha, Behnam Kia, Mohammad-Reza Jahed Motlagh, William L. Ditto

Publication date: 2 July 2008

Published in: International Journal of Bifurcation and Chaos (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1142/s0218127407018142

zbMATH Keywords

one-dimensional chaotic maps; dynamics based computing; testing systems; testing vectors

Mathematics Subject Classification ID

94C12: Fault detection; testing in circuits and networks

68M15: Reliability, testing and fault tolerance of networks and computer systems

Related Items

Controlled generation of switching dynamics among metastable states in pulse-coupled oscillator networks, Harnessing piecewise-linear systems to construct dynamic logic architecture, Chaogates: Morphing logic gates that exploit dynamical patterns, Unstable periodic orbits and noise in chaos computing, Logic from nonlinear dynamical evolution, Dynamic logic architecture based on piecewise-linear systems

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