Automatic Merge-Point Detection for Sequential Equivalence Checking of System-Level and RTL Descriptions

DOI10.1007/978-3-540-75596-8_11MaRDI QIDQ3510792zbMATH OpenOpenAlexFDO

Authors Bijan Alizadeh, Masahiro Fujita

Publication date 3 July 2008

Published in Automated Technology for Verification and Analysis (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/978-3-540-75596-8_11

zbMATH Keywords

Canonical RepresentationCommunication SystemFormal VerificationSequential Equivalence CheckingSystem on a Chip (SoC)

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60)

Recommendations

• Sequential Equivalence Checking Using a Hybrid Boolean-Word Level Decision Diagram
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Cited in

(4)

• Sequential Equivalence Checking Using a Hybrid Boolean-Word Level Decision Diagram
• Automatic Abstraction of RTL IPs into Equivalent TLM Descriptions
• Achieving high coverage in hardware equivalence checking via concolic verification
• Correct Hardware Design and Verification Methods

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