Architecture and Implementation of an Interpolation Processor for Soft-Decision Reed–Solomon Decoding

DOI10.1109/TVLSI.2007.893609MaRDI QIDQ3549245zbMATH OpenDBLPWikidataFDO

Authors Warren J. Gross, Frank R. Kschischang, P. Glenn Gulak

Publication date 21 December 2008

Published in IEEE Transactions on Very Large Scale Integration (VLSI) Systems (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/TVLSI.2007.893609

Mathematics Subject Classification ID

Decoding (94B35)

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(2)

• Towards a VLSI architecture for interpolation-based soft-decision Reed-Solomon decoders
• High-speed \(\mathrm{RS}(255, 239)\) decoder based on LCC decoding

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