Input mapping algorithm for parallel transistor structures

DOI10.1002/CTA.522MaRDI QIDQ3563567zbMATH OpenOpenAlexFDO

Authors Spiridon Nikolaidis

Publication date 31 May 2010

Published in International Journal of Circuit Theory and Applications (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1002/cta.522

zbMATH Keywords

parallel structureanalytical modelsCMOS gatesinput mapping algorithm

Mathematics Subject Classification ID

Analytic circuit theory (94C05) Software, source code, etc. for problems pertaining to information and communication theory (94-04)

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Cites work

• Analysing the operation of the basic pass transistor structure
• Analytical estimation of propagation delay and short-circuit power dissipation in CMOS gates
• CMOS current-steering DAC architectures based on the triple-tail cell

Cited in

(4)

• Transistor chaining in static CMOS functional cells of arbitrary planar topology
• An algorithm for assigning multiplexer inputs
• Efficient algorithmic decomposition of transistor groups into series, bridge, and parallel combinations
• Computing Multivalued Input–Output Characteristics in the Circuits Containing Bipolar Transistors

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