Schedule verification and synthesis for embedded real-time components

DOI10.1007/978-1-4020-6254-4_11MaRDI QIDQ3564026zbMATH OpenOpenAlexFDO

Authors Purandar Bhaduri

Publication date 2 June 2010

Published in Next Generation Design and Verification Methodologies for Distributed Embedded Control Systems (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/978-1-4020-6254-4_11

zbMATH Keywords

component-based embedded real-time systemsreal-time schedulingschedule synthesistimed gamestimed interfaces

Mathematics Subject Classification ID

Synthesis problems (93B50) Time-scale analysis and singular perturbations in control/observation systems (93C70) Automated systems (robots, etc.) in control theory (93C85) Application models in control theory (93C95)

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• Schedulability verification of embedded system AADL model based on timed automata
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• Toward parametric timed interfaces for real-time components
• Safe decomposition of startup requirements: verification and synthesis
• Verification and synthesis of interconnected embedded control systems under timing contracts
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• Virtual integration of real-time systems based on resource segregation abstraction
• Time-budgeting: a component based development methodology for real-time embedded systems
• Formal verification of real-time systems with preemptive scheduling

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