Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs
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Publication:3583462
DOI10.1007/978-3-642-15031-9_18zbMath1297.94068MaRDI QIDQ3583462
Kris Gaj, Marcin Rogawski, Ekawat Homsirikamol
Publication date: 17 August 2010
Published in: Cryptographic Hardware and Embedded Systems, CHES 2010 (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1007/978-3-642-15031-9_18
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