The glitch PUF: a new delay-PUF architecture exploiting glitch shapes

DOI10.1007/978-3-642-15031-9_25zbMATH Open1312.94095OpenAlexW1607844737MaRDI QIDQ3583472FDOQ3583472

Authors: Daisuke Suzuki, Koichi Shimizu 

Publication date: 17 August 2010

Published in: Cryptographic Hardware and Embedded Systems, CHES 2010 (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/978-3-642-15031-9_25

Recommendations

• Predictive aging of reliability of two delay PUFs
• Performance and Security Evaluation of AES S-Box-Based Glitch PUFs on FPGAs
• Photonic side-channel analysis of arbiter PUFs
• Physical characterization of arbiter PUFs
• Efficient power and timing side channels for physical unclonable functions

Mathematics Subject Classification ID

Cryptography (94A60)

Cited In (5)

• Predictive aging of reliability of two delay PUFs
• mrPUF: a novel memristive device based physical unclonable function
• Priority arbiter PUF: analysis
• Reflection Cryptanalysis of PRINCE-Like Ciphers
• Performance and Security Evaluation of AES S-Box-Based Glitch PUFs on FPGAs

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