The glitch PUF: a new delay-PUF architecture exploiting glitch shapes

DOI10.1007/978-3-642-15031-9_25MaRDI QIDQ3583472zbMATH OpenOpenAlexFDO

Authors Daisuke Suzuki, Koichi Shimizu

Publication date 17 August 2010

Published in Cryptographic Hardware and Embedded Systems, CHES 2010 (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/978-3-642-15031-9_25

Mathematics Subject Classification ID

Cryptography (94A60)

Recommendations

• Predictive aging of reliability of two delay PUFs
• Performance and Security Evaluation of AES S-Box-Based Glitch PUFs on FPGAs
• Photonic side-channel analysis of arbiter PUFs
• Physical characterization of arbiter PUFs
• Efficient power and timing side channels for physical unclonable functions

Cited in

(5)

• Predictive aging of reliability of two delay PUFs
• mrPUF: a novel memristive device based physical unclonable function
• Priority arbiter PUF: analysis
• Reflection Cryptanalysis of PRINCE-Like Ciphers
• Performance and Security Evaluation of AES S-Box-Based Glitch PUFs on FPGAs

This page was built for publication: The glitch PUF: a new delay-PUF architecture exploiting glitch shapes

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q3583472)