Applying Logic Synthesis for Speeding Up SAT

DOI10.1007/978-3-540-72788-0_26zbMath1214.68351OpenAlexW2126662120MaRDI QIDQ3612472

Alan Mishchenko, Niklas Een, Niklas Sörensson

Publication date: 10 March 2009

Published in: Theory and Applications of Satisfiability Testing – SAT 2007 (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/978-3-540-72788-0_26

Mathematics Subject Classification ID

Related Items (9)

SAT-Based Model Checking ⋮ Simulating circuit-level simplifications on CNF ⋮ Mining definitions in Kissat with Kittens ⋮ Solving SAT (and MaxSAT) with a quantum annealer: foundations, encodings, and preliminary results ⋮ Computing Storyline Visualizations with Few Block Crossings ⋮ SAT solver management strategies in IC3: an experimental approach ⋮ SAT-Based Model Checking without Unrolling ⋮ Heuristic NPN Classification for Large Functions Using AIGs and LEXSAT ⋮ Synthesis of Domain Specific CNF Encoders for Bit-Vector Solvers

Uses Software

• MiniSat

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