A Versatile Reconfigurable Bit-Serial Multiplier Architecture in Finite Fields GF(2m)
From MaRDI portal
Publication:3628444
DOI10.1007/978-3-540-89985-3_28zbMath1188.68097MaRDI QIDQ3628444
Morteza Nikooghadam, Ali Zakerolhosseini, Ehsan Malekian
Publication date: 20 May 2009
Published in: Communications in Computer and Information Science (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1007/978-3-540-89985-3_28
irreducible polynomial; elliptic curve cryptography; linear feedback shift register; Galois field; bit-serial multiplier
68M99: Computer system organization
Cites Work