Axioms for memory access in asynchronous hardware systems
From MaRDI portal
Publication:3723682
DOI10.1145/5001.5007zbMATH Open0593.68017OpenAlexW2070356883WikidataQ114613786 ScholiaQ114613786MaRDI QIDQ3723682FDOQ3723682
Authors:
Publication date: 1986
Published in: ACM Transactions on Programming Languages and Systems (Search for Journal in Brave)
Full work available at URL: http://www.acm.org/pubs/contents/journals/toplas/1986-8/
Recommendations
Cited In (21)
- Introduction à l'algorithmique des objets partagés
- Leveraging access mode declarations in a model for memory consistency in heterogeneous systems
- Data-race and concurrent-write freedom are undecidable.
- Causal memory: definitions, implementation, and programming
- Asynchronous PRAMs with memory latency
- The behavior of shared objects: Concept, pitfalls, and a new model
- Linearizable read/write objects
- A simple object that spans the whole consensus hierarchy
- Atomic read/write memory in signature-free Byzantine asynchronous message-passing systems
- On interprocess communication. II: Algorithms
- Analyzing linearizability violations in the presence of read-modify-write operations
- Time and space optimal implementations of atomic multi-writer register
- Title not available (Why is that?)
- Schedulers and finishers: on generating and filtering the behaviours of an event structure
- Schedulers and finishers: on generating the behaviours of an event structure
- Computing \(k\)-atomicity in polynomial time
- Relationships between memory models
- A criterion for atomicity
- Proof of correctness of Ressel's adopted algorithm
- Composite registers
- Concurrent Kleene Algebra
This page was built for publication: Axioms for memory access in asynchronous hardware systems
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q3723682)