Queueing modeling of a single processor with failures
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Publication:3820000
DOI10.1016/0166-5316(89)90034-5zbMath0667.68049OpenAlexW2042138309MaRDI QIDQ3820000
Publication date: 1989
Published in: Performance Evaluation (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1016/0166-5316(89)90034-5
Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Theory of operating systems (68N25)
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Two load sharing processors with failures ⋮ A time-non-homogeneous double-ended queue with failures and repairs and its continuous approximation ⋮ Queues with interruptions: a survey ⋮ A discrete-time queueing model of EMD policy in high-speed networks ⋮ Performance evaluation of CAI and RAI transmission modes in a \(GI-G-1\) queue ⋮ Analysis of a discrete-time \(GI-G-1\) queueing model subjected to bursty interruptions
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