Detection and Location of Input and Feedback Bridging Faults Among Input and Output Lines

DOI10.1109/TC.1980.1675613zbMATH Open0436.94037MaRDI QIDQ3877572FDOQ3877572

Authors: M. G. Karpovsky, S. Y. H. Su 

Publication date: 1980

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

zbMATH Keywords

fault detectionoscillationtest generationmultiple faultsfault locationundetectabilitybridging faultssingle faultscombinational networksasynchronous behaviorshort circuit failures

Mathematics Subject Classification ID

Cited In (4)

• A systematic technique for detecting and locating bridging and stuck-at faults in I/O pins of LSI/VLSI chips
• Checkpoint management with double modular redundancy based on the probability of task completion
• Friedman's question: Detectability of bridging faults in irredundant computational logic networks
• Complete test-set generation for bridging faults in combinational-logic circuits

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