An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
From MaRDI portal
Publication:3904532
DOI10.1109/TC.1981.1675757zbMath0455.94038MaRDI QIDQ3904532
Publication date: 1981
Published in: IEEE Transactions on Computers (Search for Journal in Brave)
Related Items
Forecasting the efficiency of test generation algorithms for combinational circuits, Thread-parallel integrated test pattern generator utilizing satisfiability analysis, Selective I/O scan: A diagnosable design technique for VLSI systems, Constraint satisfaction using constraint logic programming, Confidence intervals for expected coverage from a beta testability model, A complete critical path algorithm for test generation of combinational circuits, Unnamed Item