scientific article; zbMATH DE number 3748388

MaRDI QIDQ3932272zbMATH OpenFDO

Authors Peter M. Kogge

Publication date 1981

zbMATH Keywords

arithmetic pipelinecollision vectordata-stationary controldynamic pipelinegreedy strategyhierarchical memory structureinitiation latencyinstruction partitioninginterinstruction dependencelatency cyclemaximum-rate pipelinepipeline controlpipeline performancepipeline with feedbackreservation tablescheduling strategystate diagramstatic pipelinetime-stationary controlvector addressing modevector processor

Mathematics Subject Classification ID

Research exposition (monographs, survey articles) pertaining to computer science (68-02) Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Theory of software (68N99) Specification and verification (program logics, model checking, etc.) (68Q60)

Cited in

(6)

• Test schedules for VLSI circuits having built-in test hardware
• A performance study of buffered pseudorandomly interleaved memories with multiple sections
• Study of a NP-hard cyclic scheduling problem: The recurrent job-shop
• An integrated Prolog architecture for symbolic and numeric executions
• On scheduling cycle shops: Classification, complexity and approximation
• Complexity of optimal vector code generation

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